"機械学習を使った今までにないデバイスをあまねく世に広める"を企業理念に、独自のディープラーニングモデルの軽量化技術や専用回路設計技術と150を超える企業との共創で得た知見を活かし、事業を展開しています。 私たちが開発したコア製品である”Efficiera"は、独自のディープラーニングモデル軽量化手法「極小量子化技術」を最大限に活かす、FPGAデバイス上もしくはASICデバイス上の回路として動作するCNNの推論演算処理に特化した超低消費電力AI推論アクセラレータIPで、今までAIが使えなかったような環境でもdeep learningによる高度な情報処理を可能にします。 超低消費電力AIアクセラレータIP EFFICIERA https://leapmind.io/business/ip/ LeapMind Inc. is developing its business with the company mission, “to create innovative devices with machine learning and make them available everywhere” and our original weight reduction technology for deep learning models, the dedicated circuit design, and leveraging the knowledge gained from the collaboration with more than 150 companies. Our core product "Efficiera" is an ultra-low power AI inference accelerator that can be implemented on an FPGA device or ASIC/ASSP device, and is specialized for CNN inference operations, taking full advantage of our original deep learning model weight reduction method "extremely low bit quantization". It will enable advanced data processing by deep learning in environments where AI could not be used before. Ultra low power AI inference accelerator IP EFFICIERA https://leapmind.io/en/business/ip/

■Our mission 機械学習を使った今までにないデバイスをあまねく世に広める To create innovative devices with machine learning and make them available everywhere ■Our vision 次世代の情報端末を実現するためのキーテクノロジーを提供する To provide key technologies to bring next-generation information devices into reality 我々が目指す世界は人々の生活を便利に豊かにしていくものでありこれが実現できれば世界を変えられると信じています。 The world we target for is to make people’s lives more convenient and prosperous, and we believe if we realize this we can change the world.

Business Approach ・これまでの研究開発から、エッジAIの実装という課題に対して超低消費電力AI推論アクセラレータIP Efficieraを開発し、それを使ったソリューション提供を拡大している。 ・顧客のステージごとにソリューションをパッケージ+カスタマイズし、あらゆる顧客へ提供できる。 ・We are expanding our solution offering using Efficiera, an ultra low power AI inference accelerator IP, which we developed from our past research and development, to address the challenge of implementing edge AI. ・We can offer solutions for various customers by packaging and customizing solutions for each customer stage. Technological Approach ・EfficieraはLeapMindが独自に開発した極小量子化技術 を用いることで、優れた電力効率・面積効率を実現し、 AI搭載製品の省電力化・低コスト化に貢献します。 ・極少量子化技術とは、これ以上量子化ビット数を減らしてしまうとディープラーニングとして成立しない限界のビット数、つまりweightを1ビット、activationを2ビットで表現する量子化のことです。 ・Efficiera achieves superior power and area efficiency by using LeapMind's proprietary developed technology, the extremely low bit quantization, and it contributes to power savings and lower costs for AI-equipped products. ・The extremely low bit quantization is a quantization technique that expresses weight with 1 bit and activation with 2 bits, which is the limit of the number of bits that cannot be used for deep learning if the number of quantization bits is further reduced. Human Resource Approach ・LeapMindでは、社員の多様な働き方をサポートするための制度づくりに取り組んでいます。 ・社員一人一人のCareer Growthのため、1on1やContinuous Feedbackなどを実施し、メンバーの成長をサポートしています。 ・年齢やポジション、性別をはじめ、国籍、人種などを問わず、誰もが平等に仕事のできる環境を整えています。 ・私たちは、能力とスキルを最大限に活かしたい人、多様性を尊重できる人と一緒に働きたいと思っています。 ・At LeapMind, we are working to create an inclusive working environment that supports the diverse work styles of our employees. ・We support our members' growth through 1 on 1 and continuous feedback to help each employee achieve career growth. ・We provide an equal work environment for everyone, regardless of age, position, gender, nationality, or race, etc. ・We want to work with people who want to make the most of their abilities and skills, and who respect diversity. 会社紹介資料 / Company introduction slide: https://speakerdeck.com/leapmind

仕事内容/Job Description We, LeapMind Inc., are working on developing software stack to implement deep learning on low power FPGAs. In this position, you will be responsible for designing the hardware accelerator for Blueoil. The main work is RTL design, but also includes architecture design, RTL verification, logic synthesis, timing closure, area and power optimization, and IP validation with FPGA boards. 必須スキル/Required Skills ・MS degree in EECS or related technical fields, or equivalent practical experience. ・RTL design and verification in ASIC/FPGA design. ・Logic synthesis and timing closure in ASIC/FPGA design ・More than 1 year of programming experience in C or C++. ・Proficiency with Linux development environment ・Communication in English or Japanese 歓迎するスキル/Desired Skills ・Ph.D. degree in EECS or related technical fields, or equivalent practical experience. ・Over 3 years of relevant work experience, including industry experience or as a researcher in a lab. ・Experience in collaboration and project management with partners in ASIC development and volume production. ・Layout in ASIC design. ・Device driver, OS kernel code, boot code, diagnostics. ・Design, bring up, debug evaluation board. ・Experience with embedded system development. ・Experience with developing or contributing deep learning framework. ・Experience with compiler development. ・Experience with parallel programming. ・Experience in team development and/or OSS projects